An integrated circuit may include a silicon controlled rectifier (SCR) having a vertical stack of an n-type heavily doped layer, a p-type well layer and an n-type deep well layer. The SCR may be, for example, part of an electrostatic discharge (ESD) protection circuit. A bipolar gain of the vertical stack is controlled by a doping density and thickness of the p-type well layer. The p-type well layer may be formed concurrently with other p-type well layers in the integrated circuit, for example p-type well layers under n-channel metal oxide semiconductor (NMOS) transistors. Forming the p-type layers to simultaneously provide a desired bipolar gain in the SCR and provide a desired level of off-state current in the NMOS transistors may be problematic.